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| (R) L6574 CFL/TL BALLAST DRIVER PREHEAT AND DIMMING HIGH VOLTAGE RAIL UP TO 600V dV/dt IMMUNITY 50 V/ns IN FULL TEMPERATURE RANGE DRIVER CURRENT CAPABILITY: 250mMA SOURCE 450mA SINK SWITCHING TIMES 80/40ns RISE/FALL WITH 1nF LOAD CMOS SHUT DOWN INPUT UNDER VOLTAGE LOCK OUT PREHEAT AND FREQUENCY SHIFTING TIMING SENSE OP AMP FOR CLOSED LOOP CONTROL OR PROTECTION FEATURES HIGH ACCURACY CURRENT CONTROLLED OSCILLATOR INTEGRATED BOOTSTRAP DIODE CLAMPING ON VS. SO16, DIP 16 PACKAGE DESCRIPTION In order to ensure voltage ratings in excess of 600V, the L6574 is manufactured with BCD OFF LINE technology, which makes it well suited for lamp ballast applications. BLOCK DIAGRAM SO16N DIP16 ORDERING NUMBERS: L6574D L6574 The device is intended to drive two power MOSFETS, in the classical half bridge topology, ensuring all the features needed to drive and properly control a fluorescent bulb. A dedicated timing section in the L6574 allows the user set the necessary parameters for proper preheat and ignition of the lamp. Also, an OP AMP is available to implement closed loop control of the lamp current during normal lamp burning. An integrated bootstrap section, eliminating the normally required bootstrap diode and the zener clamping on Vs, makes the L6574 well suited for low cost applications where few additional components are needed to build a high performance ballast. H.V. VS OP AMP OPOUT OPINOPIN+ OUT Imin VREF DEAD TIME Ifs Imax VREF + R PRE CONTROL LOGIC Vthpre + VTHE EN2 VTHE EN1 Ipre DRIVING LOGIC LEVEL SHIFTER VS LVG RING LVG DRIVER GND VBOOT + UV DETECTION BOOTSTRAP DRIVER HVG DRIVER HVG CBOOT LOAD + - + - VCO Cf C PRE D97IN493A February 2000 1/9 L6574 PIN CONNECTION CPRE RPRE CF RING OPOUT OPINOPIN+ EN1 1 2 3 4 5 6 7 8 D97IN492 16 15 14 13 12 11 10 9 VBOOT HVG OUT N.C. VS LVG GND EN2 THERMAL DATA Symbol Rth j-amb Parameter Thermal Resistance Junction to ambient Max. DIP16 80 SO16N 120 Unit C/W PINS DESCRIPTION N. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name Cpre Rpre Cf Ring OPout OPinOPin+ EN1 EN2 GND LVG Vs N.C. OUT HVG Vboot Preheat Timing Capacitor Maximum Oscillation Frequency Setting. Low Impedence Voltage Source. See also Cf Oscillator Frequency Setting (see also Ring, Rpre) Minimum Oscillation Frequency Setting. Low Impedence Voltage Source. See also Cf Sense OP AMP Output. Low Impedence Sense OP Amp Inverting Input. High Impedence Sense OP AMP Non Inverting Input High Impedence. Half Bridge Enable Half Bridge Enable Ground Low Side Driver Output Supply Voltage with Internal Zener Clamp. Non Connected High Side Driver Reference High Side Driver Output Bootstrapped Supply Voltage Function 2/9 L6574 ABSOLUTE MAXIMUM RATINGS Symbol IS VLVG V OUT VHVG V BOOT dV BOOT/dt dV OUT/dt Vir Vic VEN1, VEN2 IEN1, IEN2 V opc Vopd Vopo Tstg, Tj Tamb Parameter Supply Current (*) Low Side Output High Side Reference High Side Output Floating Supply Voltage VBOOT pin Slew rate (repetitive) OUT pin Slew Rate (repetitive) Forced Input Voltage (pins Ring, Rpre) Forced Input Voltage (pins Cpre, Cf) Enable Input Voltage Enable Input Current Sense Op Amp Common Mode Range Sense Op Amp Differential Mode Range Sense Op Amp Output Voltage (forced) Storage Temperature Ambient Temperature Value 25 -0.3 to Vs +0.3 -1 to VBOOT -18 -1 to VBOOT -1 to 618 50 50 -0.3 to 5 -0.3 to 5 -0.3 to 5 3 -0.3 to 5 5 4.6 -40 to +150 -40 to +125 Unit mA V V V V V/ns V/ns V V V mA V V V C C (*) The device has an internal Clamping Zener between GND and the Vcc pin, it must not be supplied by a Low Impedance Voltage Source. Note: ESD immunity for pins14, 15 and 16 is guaranteed up to 900V (Human Body Model) RECOMMENDED OPERATING CONDITIONS Symbol VS VOUT (*) VBOOT (*) Supply Voltage High Side Reference Floating Supply Voltage Parameter Value 10 to VCL -1 to VBOOT-VCL 500 Unit V V V (*) If the condition Vboot - Vout < 18 is guaranteed, Vout can range from -3 to 580V. ELECTRICAL CHARACTERISTICS (VS = 12V; VBOOT-VOUT = 12V; Tamb = 25C) Symbol Vsuvp Vsuvn Vsuvh Vcl Isu Iq Pin 12 Parameter Vs Turn On Threshold Vs Turn Off Threshold Supply Voltage Under Voltage Hysteresys Supply Voltage Clamping Start Up Current VS < Vsuvn Vs > Vsup v 2 14.6 Test Condition Min. 9.5 7.3 Typ. 10.2 8 2.2 15.6 16.6 250 Max. 10.9 8.7 Unit V V V V A mA Supply Voltage Quiescent Current, fout = 60kHz, no load. High voltage Section Ibootleak Ioutleak Ihvgso Ihvgsi Ihvgso Ilvgsi trise tfall 16 14 15 15 11 11 15, 11 BOOT pin leakage current OUT pin Leakage Current High Side Driver Source Current High Side Driver Sink Current Low Side Drive Source Current Low Side Drive Source Current Low/High Side Output Rise Time Low/High Side Output Fall Time VBOOT = 580V VOUT = 562V VHVG-VOUT = 0 VHVG-VBOOT = 0 VLVG-GND = 0 VLVG-VS = 0 Cload = 1nF Cload = 1nF 170 300 170 300 250 450 250 450 80 50 5 5 A A mA mA mA mA High/Low Side Drivers 120 80 ns ns 3/9 L6574 ELECTRICAL CHARACTERISTICS (Continued) Symbol Oscillator DC fing fpre 14 Output Duty Cycle Minimum Output Oscillation Frequency Maximum Output Oscillation Frequency 2,4 14 Voltage to current converters threshold Dead Time between Low and High Side Conduction Pre Heat Timing constant Frequency Shift Timing Constant Pre Heat Timing Comparator Threshold 6,7 5 Input Bias current Input Offset Voltage Ouput Resistance Sink Output Current Source Output Current 6,7 Common Mode Input Range Sense Op Amp Gain Band Width Product DC Open Loop Gain 8,9 Enabling Comparators Threshold Enabling Comparators Hysteresis Minimum Pulse lenght 0.56 20 200 Vout = 0.2V Vout = 4.5V -10 200 0.5 0.5 -0.2 1 80 0.6 0.64 100 3 Cpre = 330nF Cpre = 330nF 0.8 CF = 470pF; Ring = 50k CF = 470pF; Ring = 50k; Rpre = 47k 48 58.2 114 50 60 120 52 61.8 126 % kHz kHz Pin Parameter Test Condition Min. Typ. Max. Unit Vref td 2 1.25 1.7 V s Timing Section kpre kfs Vthpre Sense OP AMP lib Vio R out Iout + Iout Vic GBW Gdc Comparators Vthe Vhye tpulse V mV ns 0.1 10 300 A mV mA mA V MHz dB 1 1.15 0.115 3.3 1.5 0.15 3.5 1.85 0.185 3.7 s/F s/F V High/Low Side Driving Section: High and low side driving sections provide the proper drive to the external power MOSFET. A high sink/source driving current (450/250 mA typical) ensures fast switching times when a size 4 external power MOSFET needs to be driven. Bootstrap Section: A patented integrated bootstrap section replaces an external bootstrap diode. This section together with a bootstrap capacitor provides the bootstrap voltage to drive the high side power MOSFET. This function is achieved using a high voltage DMOS driver which is driven synchronously with the low side external power MOSFET. For a safe operation, current flow into the Vboot pin is inhibited, even though ZVS operation may not be ensured. 4/9 Timing Section: To set the proper preheat time (tpre=kpre*Cpre) for the bulb, a capacitor is connected to the Cpre pin which is charged with a fixed current. During tpre, the output is switching at fpre (see Oscillator Section). When the tpre expires, the Cpre capacitor is discharged and then recharged with a different current. This sets a second time interval tsh (0.1 times the selected preheat time tpre) during which frequency shifting from fpre to fing is performed to ensure lamp ignition. Oscillator Section: A voltage controlled oscillator, with the selected frequencies fpre and fing, drives the output half bridge. Independently selected, fpre is effective during tpre and fing is effective during normal lamp burning. When working open loop, fpre and L6574 fing are the highest and lowest allowed oscillation frequencies. Closed loop control of the lamp current under normal operation can be achieved with the L6574. This is accomplished by automatic adjustment of the oscillator frequency. The OP AMP output is fed through a resistor diode network to the Ring pin. See AN 993. OP AMP Section: The integrated OP AMP offers low output impedance, wide bandwidth, high input impedance and wide common mode range. It can be readily used to implement closed loop control (see Oscillator Section) of the lamp current. EN1, EN2 Comparators: Two CMOS comparators, with thresholds set at 0.6 V (typical) are available to implement protection methods (such as overvoltage, lamp removal, etc.). Short pulses (>200nsec) at the comparator inputs are recognized. The EN1 input (active high) forces the L6574 in the shut down state (e.g. LVG low, HVG low, oscillator stopped) in the event of an undervoltage condition. Normal operating condition is resumed after a power-off power-on sequence or when EN2 input is high. The EN2 input (active high) also restarts a preheat sequence (see timing diagrams). TIMING DIAGRAMS VSUVP VCC LVG HVG EN1 D97IN490 TIMING DIAGRAMS VCC VSUVP fOUT fPRE fING EN2 D97IN491B tPRE tSH tPRE tSH 5/9 L6574 Figure 1. fING vs. RING. fING (KHz) 100 D98IN867 Figure 2. f vs. RPRE, with RING = 33k f (KHz) RING=33K D98IN868 80 80 60 60 40 40 20 20 40 60 80 100 RING(K) 20 20 40 60 80 100 RPRE(K) Figure 3. f vs. RPRE, with RING = 50k f (KHz) RING=50K D98IN869 Figure 4. f vs. RPRE, with RING = 100k f (KHz) RING=100K D98IN870 100 100 80 80 60 60 40 40 20 20 40 60 80 100 RPRE(K) 20 20 40 60 80 100 RPRE(KH) Figure 5. fING vs. temperature. fING (KHz) D98IN871 Figure 6. fPRE vs. temperature. fPRE (KHz) D98IN872 70 130 60 120 50 110 40 -50 100 0 50 100 T(C) -50 0 50 100 T(C) 6/9 L6574 DIM. MIN. A a1 a2 b b1 C c1 D (1) E e e3 F (1) G L M S 3.8 4.6 0.4 9.8 5.8 0.35 0.19 0.1 mm TYP. MAX. 1.75 0.25 1.6 0.46 0.25 0.5 45 (typ.) 10 6.2 1.27 8.89 4 5.3 1.27 0.62 8(max.) 0.150 0.181 0.016 0.386 0.228 0.014 0.007 0.004 MIN. inch TYP. MAX. 0.069 0.009 0.063 0.018 0.010 0.020 OUTLINE AND MECHANICAL DATA 0.394 0.244 0.050 0.350 0.157 0.209 0.050 0.024 SO16 Narrow (1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch). 7/9 L6574 DIM. MIN. a1 B b b1 D E e e3 F I L Z 0.51 0.77 mm TYP. MAX. MIN. 0.020 1.65 0.5 0.25 20 8.5 2.54 17.78 7.1 5.1 3.3 1.27 0.030 inch TYP. MAX. OUTLINE AND MECHANICAL DATA 0.065 0.020 0.010 0.787 0.335 0.100 0.700 0.280 0.201 0.130 0.050 DIP16 8/9 L6574 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 9/9 |
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